EDA giant Ansys and TSMC have extended their long-term technical cooperation and announced that their power integrity software has passed the certification of TSMC’s FINFLEX innovation and TSMC’s N4 process. TSMC’s FINFLEX architecture enables Ansys RedHawk-SC and Totem customers to make subtle speed and power tradeoffs without sacrificing performance to reduce die power consumption. This is important for lowering the environment for many semiconductor applications, including applications such as machine learning (ML), 5G mobility, and high-performance computing (HPC). This latest collaboration builds on Ansys’ recent platform benchmark via TSMC’s N3E process.
Dan Kochpatcharin, Director of TSMC’s Design Infrastructure Management Group, said the unprecedentedly flexible FINFLEX innovation offers many die design benefits and flexibility that can be optimized for high performance, low power consumption, or a balance between the two. Our latest collaboration with Ansys on TSMC’s 3nm technology enables our mutual customers to easily take advantage of FINFLEX with confidence in the power integrity and robust signoff verification results of RedHawk-SC and Totem.
Based on TSMC’s N3E process technology, TSMC’s FINFLEX architecture enables chip designers to choose from three FIN configurations when implementing each standard component: one for highest performance and fastest clock frequency; another for balancing effective performance; Finally, there’s a superpower for the lowest leakage and highest density. This combination of features enables wafer designers to use the same combination of design tools to select the best combination of speed and performance for each critical functional block on the wafer.
Ansys has developed an integrated software platform of multiphysics simulation and analysis tools with a focus on power management to minimize the design and operation of semiconductors costs. Our ongoing collaboration with TSMC aligns with our goal of achieving a sustainable future, enabling mutual customers to increase chip performance while reducing power consumption.
